Featuring LDPC ECC and technologies such as high TBW (total bytes written) and DEVSLP (Device Sleep), the Ultimate SU800 instantly upgrades notebook and desktop PCs with superior stability, durability, and power efficiency. A Memory Efficient FPGA Implementation of Quasi-Cyclic LDPC Decoder JIN SHA, MINGLUN GAO, ZHONGJIN ZHANG,LI LI Institute of VLSI design Key Laboratory of Advanced Photonic and Electronic Materials Nanjing University Nanjing, China, 210093 ZHONGFENG WANG School of EECS Oregon State University Corvallis, OR 97331-5501,USA Proposed V-LDPC Read data HED LDPC decode Errors Detected Errors of upper page are fewer Conventional LDPC Upper Middle Lower Detected Errors Detected errors are dispersedper page Data-retention time (day) W6. ) Ý D f es) e (u.) 0 +90% 3D-TLC NAND flash, NCL = 8,NW/E = 300 Max iteration = 30, AC7, @85degC Conventional LDPC Proposed V-LDPC w ...

BCH is a less complex algorithm than LDPC, so it has a significantly smaller gate count. I was told a year ago that an LDPC ECC engine adds about $1.00 of cost to a new controller chip, but this number will shrink over time thanks to Moore’s Law. Readers who want a better understanding of LDPC can read the LDPC Wikipedia page.